`timescale 1ns / 1ps

module user_app(
    input en,
    output [7:0] led,
	 input clk
    );

reg [30:0] counter;

assign  led = counter[30:23];

always @(posedge clk)
begin
		if(en == 1'b1)
			counter <= counter + 1;
end

endmodule
